An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. These data written into the memory location are called as “rules”. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).
In a ternary CAM every bit of data has a Data and Mask bit. Data for a bit is the data that has to be compared for that bit, this data is however qualified by a mask bit which is used as a control bit for each of the data bit to enable or disable it from comparison. When the bit is masked it is called don't care bit. Following table shows a one possible data and mask scheme
NameDataMaskNo Mask01“0”No Mask11“1”Mask “0”00Mask “1”10Once information is stored in a memory location, it is found by comparing every bit in a memory location with corresponding bits in a comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, a local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which desired data is stored or identification of one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back an address if there is a match found in memory. In a ternary CAM when data with mask are stored at various locations and searches are done with a data then for a given data, there is a possibility of multiple rules getting matched for a given key. In a Ternary CAM the process of resolving multiple matches to generate a single match output is called priority resolution. There are many schemes of priority resolution two of the ones are highest order priority or lowest order priority. Highest Priority resolution is where the largest address matched is given out and the lowest order priority is where the smallest address match is given out.
FIG. 1 is a circuit diagram illustrating a conventional SRAM based ternary CAM cell 100. The CAM cell 100 includes a data storage portion 110, which is comprised of an access transistor D0 and a pair of inverters D1a, D1b, arranged in as shown in FIG. 1. The gate of the access transistor D0 is coupled to a word line WL, and one source/drain terminal of the access transistor D0 is coupled to a bit line BL. Thus, a voltage level indicative of a logical value that is placed on the bit line BL is gated across the access transistor D0 when the word line WL is high. This sets the voltage at node D to the voltage equal to the logical value. The two inverter structure D1a, D1b subsequently maintains the logical value at node D and a complement of the logical value at node D#.
A match section 120 of the CAM cell 100 is comprised of transistors M1, M1#, M2, M2# and M3, which controllably couple the match line ML to ground in certain situations. In the CAM cell 100, a “no-match” condition is detected if the match line ML remains at a precharge potential, which a “match” condition is detected if the match line ML is pulled to ground during the match operation. Typically, the detection of the state of the match line ML is performed by a sense amplifier (not illustrated).
Transistor M3 has one source/drain terminal coupled to the mach line ML and another source/drain terminal coupled to a four-transistor circuit formed by transistors M1, M1#, M2, and M2#. The gate of transistor M3 is coupled to a register M, which stores a mask value. The register M and transistor M3 are present when CAM cell 100 is a ternary CAM (TCAM) cell. TCAM cells permit the search expression to include “don't care” bits, while binary CAMs enforce a match/no-match evaluation of every bit. If CAM cell 100 were a binary CAM, transistor M3 and register M would not be present and the source/drain terminals of transistor M2 and M2# illustrated as being coupled to a source/drain terminal of transistor M3 would instead be coupled directly to the match line ML.
Transistors M1, M1#, M2, and M2# form a comparison circuit. The gates of transistors M2, M2# are respectively coupled to search data lines SD and SD#. The search data is placed on the line SD while the complement of the search data is placed on the line SD#. Similarly, the logical value stored at node D is coupled to the gate of transistor M1 while the complement of that logical value stored at node D#is coupled to the gate of transistor M1#. In this manner, the comparison structure will pull the match line ML voltage from its precharged level to ground if and only if the search data on line SD matches the data stored at node D or the complement of the search data on line SD# matches the complement of the data stored at node D, assuming that transistor M3 is conducting. If transistor M3 is not conducting, the match line ML potential will remain at its pre-charged level.
When a memory device is manufactured, it must be tested. Although testing is time consuming and costly, testing is required to identify errors in the device. If errors are not identified, the use of the memory device can corrupt data. In addition to error detection, an ideal test should also be able to inform the tester as to which portion of a CAM cell is defective. If many defects are isolated to a same problem area, the data can form the basis of improving the device fabrication process. Accordingly, there is a need for a method to efficiently test CAM cells in a CAM device and to identify which component of a defective CAM cell failed.